The demand for faster and cheaper integrated circuits is ever growing. Moore's Law posits that the number of transistors per square inch would double every year. However, as traditional two dimensional (or planar) chipmaking methods are reaching its boundaries, in order to fulfill the prophecy of Moore's Law, more innovative techniques for expanding the chipmaking frontiers are necessary.
Heretofore, most of the demand for denser integrated circuits has been met by ever shrinking active devices fabricated on a relatively planar structure. That is, two dimensional chipmaking has been the predominant method of semiconductor fabrication. Most semiconductor devices have been built in a planar monocrystalline semiconductor substrate. This approach allows only very limited vertical integration into the third dimension.
As the limitations of two dimensional chip making are approaching, major breakthroughs in performance will be derived from three dimensional chipmaking (that is, chipmaking in the z-dimension).
Vertical integration, or stacking of microdevices into the same package, is an attractive way to decrease packaging volume, to increase circuit density and to conserve board space, and to increase performance and functionality. Reductions of interchip delays and power consumption are both benefits of stacked integration. If the devices are thinned and stacked on top of each other, the advantages in cost and circuit density are potentially huge. For both IC and MEMS processes, the third dimension of the silicon wafer remains largely unexploited.
Current commercial approaches to vertical stacking of 2-dimensional devices are generally chip-scale and rely on wafer thinning by grinding. Most methods rely on interconnection by way of throughholes or wire-bonded, stacked mother-daughter chips. Current methods all have limitations with respect to package size, cost, reliability and yield impact. Despite the difficulties, stacking devices to achieve 3-D integration is finding applications, particularly in combining Micro Electromechanical Systems (“MEMS”) with Application Specific Integrated Circuits (“ASIC”) controllers. High density memory packages made by stacking individual chips have found specialty applications.
IBM U.S. Pat. No. 6,355,501 discloses a method of fabricating a three-dimensional IC assembly, generally on chip scale. Disclosed therein is assembly consisting of three dimensional stacked Silicon on Insulator (“SOI”) chips, and a method of forming such integrated circuit assembly. Each of the SOI chips includes a handler making mechanical contact to a first metalization pattern making electrical contact to a semiconductor device. The metalized pattern, in turn, contacts a second metalization pattern positioned on an opposite surface of the semiconductor device. The disclosed method includes the steps of: a) providing a substrate having a third metalized pattern on a first surface of the substrate; b) aligning one of the SOI chips on the first surface of the substrate, by having the second metalization pattern of the SOI chip make electrical contact with the third metalized pattern of the substrate; c) removing the handler from the SOI chip, exposing the first metalization pattern of the SOI chip; d) aligning a second one of the SOI chips with the first SOI chip, having the second metalization pattern of the second SOI chip make electrical contact to the exposed first metalization pattern of the first SOI chip; and e) repeating steps c) and d) for mounting subsequent SOI chips one on top of the other. However, this reference teaches a method that may be prohibitively expensive and severally functionally limited.
A key disadvantage of the method taught in the aforementioned U.S. Pat. No. 6,335,501 is that the applicants thereof note that forming three-dimension circuits on a wafer scale leads to low yield. Further, alignment of each chip is considered to be a significant problem preventing wafer scale stacking. Each chip stacking step includes alignment of the layers to be bonded to each other. Transparent adhesives and windows must be provided to allow optical access to the alignment marks on both surfaces to be bonded to each other. Further, the handler must be transparent to the alignment marks. Other disadvantages relate to the number of sequential repeated process steps. As described therein, to make electrical contract between stacked layers, a solder reflow step is performed between each layer when it is stacked and aligned. After reflow, the chip stack is edge bonded. Further, the handler must be removed by glue removal (by laser or other heating), polishing, and other preparation steps before the subsequent layer may be bonded. Finally, excess substrate is grinded or otherwise etched-back for removal.
These drawbacks lead to several disadvantages related to cost and functionality. Cost detriments are found with the grinding removal; numerous sequential steps; chip scale as opposed to wafer scale stacking, wherein wafer scale is known to reduce cost; inability to overcome yield issues on wafer scale thus reverting to chip scale; limitation of the number of layers, thus to form higher number stacks, stacks must be stacked on other stacks; overall yield is decreased because the number of sequential statistically dependant through interconnects; multiple reflow steps potentially damage other layers;. Functionality drawbacks include lack of diagnostics; lack of interconnect versatility; limited space for interconnects; limited addressability of large stack, particularly memory stack; no ability to integrate noise shielding; no ability to integrate heat dissipation; no ability of ground plane; limitation of the number of layers.
One implementation of 3-dimensional packaging has been undertaken by Irvine Sensors, Irvine, Calif., and IBM. Discrete die have been stacked and interconnected utilizing an edge lift-off process. Known-good-die (KGD) are thinned. Solder bumps at the die edge are used to align and interconnect the stacked die. The die are potted in an epoxy matrix. The epoxy helps to align different sized die, and is used as the interconnect surface. The individual stacking and interconnection of die, along with the requirement for KGD causes this to be a very expensive manufacturing method.
Another implementation of 3-dimensional packaging has been undertaken by Cubic Memory, who manufactures high-density, stacked memory modules by applying gold interconnect traces that are deposited over insulating layers of polyimide on whole wafers. However, stacking and vertical interconnect is still on an individual chip-scale.
A further implementation of 3-dimensional packaging has been undertaken by Tessera, San Jose, Calif., in conjunction with Intel, to develop chip-scale, stacked package by attaching the chips onto flexible substrates via micro-ball grid array bonding, then z-folding the chip-loaded tape onto itself.
Ziptronix is apparently developing wafer-scale stacking of ICs. Considerable challenges with alignment, stress management, thermal management, high density interconnect and yield are still being addressed.
As illustrated above, there are various deficiencies with available vertical integration. One primary deficiency is due to yield loss. All approaches to device stacking that are currently in the marketplace are die-scale. Individual die are prepared, aligned, stacked and connected. The processing is expensive and the yield loss for the stack is the compounded yield loss for each device in the layer. The increased yield loss is sometimes tolerated for inexpensive devices such as SRAM stacks. But when more expensive devices are being stacked, the solution is to use known good die (KGD). For KGD, each unpackaged die undergoes bum-in and test. Furthermore, the stack requires electrical test after the completion of each layer. The process is very expensive and the applications have been limited to high end users, such as military and satellite technology.
Another deficiency of conventional vertical integration is due to the fact that the technology is limited to a die-scale. With the exception of the yet-to-reach-the market approach of Ziptronix, all of the approaches to stacking devices are on die scale. The significant economic advantage of wafer-scale manufacturing is completely unavailable to these technologies. The high cost of handling and testing individual die restricts these methods to high-end applications.
Another problem known throughout conventional manufacturing processes forming circuits is the requirement to support the processing device on a substrate. During processing, the substrate is required to provide mechanical support and thermal stability. The processed substrate, therefore, must be sufficiently thick to withstand the harsh processing environment, including high pressures and temperatures, as well as chemical and energy exposure. Further processing is therefore required if viable thin film devices are sought.
One processing approach, undertaken after a circuit or other structure is formed on a sufficiently thick substrate to withstand processing, is to remove the thickness of the substrate by mechanical methods. These mechanical methods, such as cutting or grinding, waste a tremendous amount of material and labor. The cut or ground material often may not be recycled, or, even if it is recyclable, the material must undergo further processing before reuse. Further, the thinned substrate is generally subjected to polishing or other processes to smooth the surface. Other techniques include formation of an etch stop layer on the substrate prior to device fabrication. However, the substrate is still typically ground or otherwise mechanically removed prior to a selective etching step, which etches the substrate generally to the etch stop layer. All of these techniques result in wasted time and material, as well presenting quality control concerns.
Another technique to form thin film devices utilizes ion implantation methods. A common use of ion implantation is to generally derive thin layers of semiconductor materials. Such methods are disclosed in, for example, EP01045448 and WO00/024059, both entitled “Method of Producing SOI Wafer by Hydrogen Ion Implanting Separation Method and SOI Wafer Produced by the Method,” and both incorporated by reference herein. Particularly, ions, such as hydrogen ions or helium ions, are implanted within the top surface of an oxidized silicon wafer. The ions are implanted to a depth within the top surface. Thereafter, a thin layer may be delaminated from the bulk silicon substrate, which is generally subjected to high temperature (greater than about 500° C.) processes. This thin layer may be then supported on an insulator layer and a substrate, and microelectronics or other structures may be formed thereon. The microelectronics, however, must be formed subsequent to delaminating the thin layer, since ion implantation detrimentally affects the microelectronics. Particularly, the thin layer may be warped, the devices may be damaged by the ion implantation, or the device may be damaged during delamination.
Bruel et al. WO 98/33209, entitled “Method For Obtaining A Thin Film, In Particular Semiconductor, Comprising A Protected Ion Zone And Involving An Ion Implantation,” discloses an approach to providing a thin film including a metal oxide semiconductor (“MOS”). In general, a MOS transistor is formed on the surface of a semiconductor substrate. The region of the transistor is masked, and surrounding regions are ion implanted to define an intended line of fracture (i.e., where microbubbles develop from the ion implantation step). To separate the thin film having the transistor thereon, cleavage is commencing at the intended line of fracture in the vicinity of the microbubbles, and is propagated through the crystal plane under the transistor (i.e., where no microbubbles exist). While it may be possible to realize thin films having transistors thereon using the teachings of WO 98/33209, the transistors are subjected to undesirable stress in the cleavage propagation, since the crystalline structure of the substrate material must be fractured in the immediate vicinity of the transistor.
Aspar et al. U.S. Pat. No. 6,103,597 entitled “Method Of Obtaining A Thin Film Of Semiconductor Material,” generally teaches subjecting a thin film substrate having microelectronics or other structures therein to ion bombardment. Gaseous microbubbles are thus formed at a depth therein defining the thickness of the thin film. However, many types of microelectronics and structures that may be formed on the substrate require a subsequent annealing step, in order to repair damage or other defects imparted to the elements. Thereafter, the thin film layer is taught to be separable from the underlying substrate material by thermal treatment that causes a fracture along the line of the microbubbles.
Sakaguchi et al., U.S. Pat. No. 6,221,738 entitled “Substrate And Production Method Thereof” and U.S. Pat. No. 6,100,166 entitled “Process For Producing Semiconductor Article”, both of which are incorporated by reference herein, teach bonding a substrate to a porous semiconductor layer. The bonding at the porous layer is taught to be mechanically weaker, thus facilitating removal by application of an external force. U.S. Pat. No. 6,100,166 teaches that a layer may be removed with a force in a peeling direction. However, both of these references disclose use of the weak porous separation mechanism at the entire interface between the layers. This may compromise overall mechanical integrity of the intermediate structure and any semiconductor devices formed on the porous semiconductor material.
Henley et al., U.S. Pat. No. 6,184,111 entitled “Pre-Semiconductor Process Implant And Post-Process Film Separation,” which is incorporated by reference herein, discloses use of a stressed layer at a selected depth below a silicon water surface. Devices are formed above the stressed layer. Implantation is generally carried out at the same energy level with varying dosage across the diameter of the wafer. Controlled cleavage propagation is initiated to separate a layer above the stressed layer, including any devices thereon. It is noted that processing to form the stressed layer may damage devices formed thereon, thus subsequent repair annealing is typically required. Therefore, conventional ion implantation and delamination methods are lacking in that a thin film including microelectronics or other structures thereon may not be ion implanted without warping or other damage to the thin semiconductor.
Therefore, considering the deficiencies of present circuit processing, it would be desirable to provide a three-dimensional integrated circuit, on a chip or on a wafer scale, which avoids the drawbacks and shortcomings of the conventional approaches.
Accordingly, a primary object of the present invention is to provide a low cost three-dimensional integrated circuit.
A further object of the invention is to provide a multiple layered substrate for fabrication of a useful device.
An additional object of the invention is to provide a multiple layered substrate for fabrication of a useful device including a buried oxide layer therein.
Another object of the present invention is to provide improved alignment techniques, particularly for use with the device layer formation, removal and stacking methods herein.
It is another object of the invention is to provide improved edge interconnections.
Additionally, an object of the invention is to provide improved through interconnections.
An additional object of the invention is to provide a vertically integrated device that is capable of including shielding between layers.
An additional object of the invention is to provide a vertically integrated device that is capable of including heat dissipation between layers.
An additional object of the invention is to provide a vertically integrated device that is capable of very high numbers of interconnections, by virtue of a buffer or congestion layer.
The above and other objects and advantages of this invention will become more readily apparent when the following description is read in conjunction with the accompanying drawings.